CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 9 — Disable Master Prefetch
This bit determines the CardBus Master Prefetch behavior. (Bit position is R/W for each socket:
chip-level function, programmable in function 0 only.)
0
CardBus master prefetching from PCI memory is allowed.
1
CardBus master prefetching from PCI is disabled.
Bit 10 — D3 Disable Auto Reset — PME_CXT
This bit determines the CL-PD6833 action when the socket’s PCI function is in D3 power state.
This bit is part of the PME_CXT, a set of register bits that do not get reset or initialized if PME
Enable is true when the CL-PD6833 changes power states from D3 to D0 through a software PCI
Bus Segment reset.
0
Reset signal to cards is activated in D3 if card is powered.
1
Automatic Card Reset in D3 is disabled.
Bits 31:11 — Reserved
74
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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