CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
6.4 Event Force
Register Name: Event Force
Memory Offset: 00Ch
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Byte 3
Reserved
Bit 23
Bit 22
Bit 21
R:00000000
Bit 20
Bit 19
Bit 18
Byte 2
Reserved
Bit 15
Bit 14
Bit 13
R:00000000
Bit 12
Bit 11
Bit 10
Byte 1
Reserved CV Test
Y-V
X-V
3.3-V Card 5-V Card
Byte 0
W:0
Bit 7
Not a Card
W:0
W:0
Bit 6
W:0
Bit 5
W:0
Bit 4
W:0
Bit 3
W:0
Bit 2
Reserved
CardBus PC
Card
16-Bit PC
Card
Power Cycle
CCD2
Changed
W:0
W:0
W:0
W:0
W:0
Register Per: socket
Bit 25
Bit 24
Bit 17
Bit 16
Bit 9
Bad VCC
Request
W:0
Bit 1
CCD1
Changed
W:0
Bit 8
Data Lost
W:0
Bit 0
CSTSCHG/
WAKEUP
W:0
The Event Force register is a phantom register. These bits are merely control bits. They are not registered
and need no clearing. They provide software the ability to force various status and event bits in the
CL-PD6833. This gives software the ability to test and restore status. Writing ‘1’ to a bit in this register sets
the corresponding bit in the Status Event register and/or the Present State register. Bits 3:0 generate
Management Interrupt if the correct Mask bit is set.
Bit 0 — CSTSCHG/WAKEUP
This bit sets the Card Status Change bit in the Status Event register. The Present State register
remains unchanged.
Bit 1 — CCD1 Changed
This bit sets the CCD1 bit in the Status Event register. The Present State register remains
unchanged.
Bit 2 — CCD2 Changed
This bit sets the CCD2 bit in the Status Event register. The Present State register remains
unchanged.
Bit 3 — Power Cycle
This bit sets the Power Cycle bit in the Status Event register. The Present State register remains
unchanged.
Bit 4 — 16-Bit PC Card
This bit sets the 16-bit PC Card bit in the Present State register. If a card is installed in the socket,
writes to this bit are ignored.
80
CARDBUS REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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