CLRC63201T View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'CLRC63201T' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
9.5.1 Timer unit implementation
9.5.1.1 Timer unit block diagram
Figure 8 shows the block diagram of the timer module.
TStartTxBegin
TxBegin Event
TStartTxEnd
TxEnd Event
TAutoRestart
TRunning
RxEnd Event
TStopRxEnd
RxBegin Event
TStopRxBegin
13.56 MHz
to parallel interface
TReloadValue[7:0]
TStartNow
TStopNow
QS
QR
PARALLEL IN
START COUNTER/
PARALLEL LOAD
COUNTER MODULE
(x ≤ x − 1)
STOP COUNTER
TPreScaler[4:0]
TimerValue[7:0]
CLOCK
DIVIDER
PARALLEL OUT
Counter = 0 ?
to interrupt logic: TimerIRq
001aak611
Fig 8. Timer module block diagram
The timer unit is designed, so that events when combined with enabling flags start or stop
the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received
data with the timer unit. In addition, the first received bit is indicated by the TxBegin event.
This combination starts the counter at the defined TReloadValue[7:0].
The timer stops automatically when the counter value is equal to zero or if a defined stop
event happens.
9.5.1.2 Controlling the timer unit
The main part of the timer unit is a down-counter. As long as the down-counter value is
not zero, it decrements its value with each timer clock cycle.
If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On
reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0].
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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