CLRC63201T View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'CLRC63201T' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
9.6 Power reduction modes
9.6.1 Hard power-down
Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pads and
defined internally (except pin RSTPD itself). The output pins are frozen at a given value.
The status of all pins during a hard power-down is shown in Table 25.
Table 25. Signal on pins during Hard power-down
Symbol
Pin
Type
Description
OSCIN
1
I
not separated from input, pulled to AVSS
IRQ
2
O
high-impedance
MFIN
3
I
separated from input
MFOUT
4
O
LOW
TX1
5
O
HIGH, if bit TX1RFEn = logic 1
LOW, if bit TX1RFEn = logic 0
TX2
7
O
HIGH, only if bit TX2RFEn = logic 1 and bit
TX2Inv = logic 0
otherwise LOW
NCS
9
I
separated from input
NWR
10
I
separated from input
NRD
11
I
separated from input
D0 to D7
13 to 20
I/O
separated from input
ALE
21
I
separated from input
A0
22
I/O
separated from input
A1
23
I
separated from input
A2
24
I
separated from input
AUX
27
O
high-impedance
RX
29
I
not changed
VMID
30
RSTPD
31
A
pulled to VDDA
I
not changed
OSCOUT
32
O
HIGH
9.6.2 Soft power-down mode
Soft power-down mode is entered immediately using the Control register bit PowerDown.
All internal current sinks, including the oscillator buffer, are switched off. The digital input
buffers are not separated from the input pads and keep their functionality. In addition, the
digital output pins do not change their state.
After resetting the Control register bit PowerDown, the bit indicating Soft power-down
mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The
PowerDown bit is automatically cleared when the Soft power-down mode is exited.
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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