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CLRC63201T View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
MFG CO.
CLRC63201T
NXP
NXP Semiconductors. NXP
'CLRC63201T' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
Remark: Pin MFIN can only be accessed at 106 kBd based on ISO/IEC 14443 A. The
Manchester signal and the Manchester signal with subcarrier can only be accessed on pin
MFOUT at 106 kBd based on ISO/IEC 14443 A.
9.11.1 Serial signal switch block diagram
Figure 14 shows the serial signal switches. Three different switches are implemented in
the serial signal switch enabling the CLRC632 to be used in different configurations.
The serial signal switch can also be used to check the transmitted and received data
during the design-in phase or for test purposes. Section 15.2.1 on page 110 describes the
analog test signals and measurements at the serial signal switch.
Remark: The SLR400 uses pin name SIGOUT for pin MFOUT. The CLRC632
functionality includes the test modes for the SLRC400 using pin MFOUT.
serial data out
MILLER CODER
1 OUT OF 256
NRZ OR
1 OUT OF 4
(part of)
serial data processing
serial data in
MANCHESTER
DECODER
00
1 internal
2 Manchester with subcarrier
3 Manchester
2
Decoder
Source[1:0]
SUBCARRIER
DEMODULATOR
00
11
envelope 2
MFIN 3
TX1
MODULATOR
DRIVER
TX2
2
Modulator
Source[1:0]
(part of)
analog circuitry
Manchester out
SUBCARRIER
DEMODULATOR
CARRIER
DEMODULATOR
RX
SERIAL SIGNAL SWITCH
3 MFOUTSelect[2:0]
01
digital test signal
signal to MFOUT
Fig 14. Serial signal switch block diagram
MFIN
MFOUT
001aak617
Section 9.11.2, Section 9.11.2.1 and Section 9.11.2.2 describe the relevant registers and
settings used to configure and control the serial signal switch.
9.11.2 Serial signal switch registers
The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal
Manchester decoder and are described in Table 30.
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
38 of 127
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