CLRC63201T View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'CLRC63201T' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
Table 30. DecoderSource[1:0] values
See Table 96 on page 67 for additional information.
Number DecoderSource Input signal to decoder
[1:0]
0
00
constant 0
1
01
output of the analog part. This is the default configuration
2
10
direct connection to pin MFIN; expects an 847.5 kHz subcarrier
signal modulated by a Manchester encoded signal
3
11
direct connection to pin MFIN; expects a Manchester encoded
signal
The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the
transmitted 13.56 MHz energy carrier. The modulated signal drives pins TX1 and TX2.
Table 31. ModulatorSource[1:0] values
See Table 96 on page 67 for additional information.
Number ModulatorSource Input signal to modulator
[1:0]
0
00
constant 0 (energy carrier off on pins TX1 and TX2)
1
01
constant 1 (continuous energy carrier on pins TX1 and TX2)
2
10
modulation signal (envelope) from the internal encoder. This is the
default configuration.
3
11
direct connection to MFIN; expects a Miller pulse coded signal
The MFOUTSelect register MFOUTSelect[2:0] bits select the output signal which is to be
routed to pin MFOUT.
Table 32. MFOUTSelect[2:0] values
See Table 110 on page 70 for additional information.
Number MFOUTSelect Signal routed to pin MFOUT
[2:0]
0
000
constant LOW
1
001
constant HIGH
2
010
modulation signal (envelope) from the internal encoder
3
011
serial data stream to be transmitted; the same as for
MFOUTSelect[2:0] = 001 but not encoded by the selected pulse
encoder
4
100
output signal of the receiver circuit; card modulation signal
regenerated and delayed
5
101
output signal of the subcarrier demodulator; Manchester coded card
signal
6
110
reserved
7
111
reserved
To use the MFOUTSelect[2:0] bits, the TestDigiSelect register SignalToMFOUT bit must
be logic 0.
9.11.2.1 Active antenna concept
The CLRC632 analog and digital circuitry is accessed using pins MFIN and MFOUT.
Table 33 lists the required settings.
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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