CLRC63201T View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'CLRC63201T' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
10.3 Register overview
Table 39. CLRC632 register overview
Sub
Register name
address
(Hex)
Function
Refer to
Page 0: Command and status
00h
Page
selects the page register
Table 41 on page 50
01h
Command
starts and stops command execution
Table 43 on page 50
02h
FIFOData
input and output of 64-byte FIFO buffer
Table 45 on page 51
03h
PrimaryStatus
receiver and transmitter and FIFO buffer status flags
Table 47 on page 51
04h
FIFOLength
number of bytes buffered in the FIFO buffer
Table 49 on page 52
05h
SecondaryStatus
secondary status flags
Table 51 on page 53
06h
InterruptEn
enable and disable interrupt request control bits
Table 53 on page 53
07h
InterruptRq
interrupt request flags
Table 55 on page 54
Page 1: Control and status
08h
Page
selects the page register
Table 41 on page 50
09h
Control
control flags for timer unit, power saving etc
Table 57 on page 55
0Ah
ErrorFlag
show the error status of the last command executed
Table 59 on page 55
0Bh
CollPos
bit position of the first bit-collision detected on the RF interface Table 61 on page 56
0Ch
TimerValue
value of the timer
Table 63 on page 57
0Dh
CRCResultLSB
LSB of the CRC coprocessor register
Table 65 on page 57
0Eh
CRCResultMSB
MSB of the CRC coprocessor register
Table 67 on page 57
0Fh
BitFraming
adjustments for bit oriented frames
Table 69 on page 58
Page 2: Transmitter and coder control
10h
Page
selects the page register
Table 41 on page 50
11h
TxControl
controls the operation of the antenna driver pins TX1 and TX2 Table 71 on page 59
12h
CwConductance
selects the conductance of the antenna driver pins TX1 and TX2 Table 73 on page 60
13h
ModConductance
defines the driver output conductance
Table 75 on page 60
14h
CoderControl
sets the clock frequency and the encoding
Table 77 on page 61
15h
ModWidth
selects the modulation pulse width
Table 79 on page 62
16h
ModWidthSOF
selects the SOF pulse-width modulation (I-CODE1 fast mode) Table 81 on page 62
17h
TypeBFraming
defines the framing for ISO/IEC 14443 B communication
Table 83 on page 63
Page 3: Receiver and decoder control
18
Page
selects the page register
Table 41 on page 50
19
RxControl1
controls receiver behavior
Table 85 on page 64
1A
DecoderControl
controls decoder behavior
Table 87 on page 65
1B
BitPhase
selects the bit-phase between transmitter and receiver clock Table 89 on page 65
1C
RxThreshold
selects thresholds for the bit decoder
Table 91 on page 66
1D
BPSKDemControl controls BPSK receiver behavior
Table 93 on page 66
1Eh
RxControl2
controls decoder and defines the receiver input source
Table 95 on page 67
1Fh
ClockQControl
clock control for the 90 phase-shifted Q-channel clock
Table 97 on page 67
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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