ADM Codec
CMX649
CLK DIVIDER CONTROL Register ($72)
Pre-Scaler
Enable
(Bit 15)
Setting this bit to a logic 1 enables the pre-scaler divider.
Decode Bit
Clock Enable
(Bit 14)
Setting this bit to a logic 1 enables the decode bit clock.
Encode Bit
Clock Enable
(Bit 13)
Setting this bit to a logic 1 enables the encode bit clock.
Filter Clock Pre-
Scaler
(Bits 12 – 11)
These bits control the internal switched capacitor filter clock pre-scaler.
Bit 12
0
0
1
1
Bit 11
0
1
0
1
Divider Ratio
1
2
3
4
Filter Clock
Divider
(Bits 10 – 8)
These bits control the internal switched capacitor filter clock divider.
Bit 10
0
0
0
0
1
1
1
1
Bit 9
0
0
1
1
0
0
1
1
Bit 8
0
1
0
1
0
1
0
1
Divider Ratio
2.000
8.000
15.500
15.750
16.000
22.000
31.250
46.750
Bit Clock Pre-
Scaler
(Bits 7 – 6)
These bits control the bit clock pre-scaler.
Bit 7
0
0
1
1
Bit 6
0
1
0
1
Divider Ratio
1
2
3
4
© 2003 CML Microsystems Plc
22
D/649/2