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CMX649 View Datasheet(PDF) - CML Microsystems Plc

Part Name
Description
MFG CO.
CMX649
CML
CML Microsystems Plc CML
'CMX649' PDF : 50 Pages View PDF
ADM Codec
CMX649
Data Filter
Bandwidth
(Bit 0)
Setting this bit to a logic 1 forces the data filter to narrow bandwidth mode.
CODEC INTERRUPT CONTROL Register ($81)
Encoder Control
(Bits 7 – 4)
Bit 7 Bit
6
0
X
1
0
1
1
1
X
1
X
Bit 5 Bit 4
Encoder Setting
X
X Encoder is disabled and reset.
0
0 Encoder is enabled to run without generating IRQs.
X
X Encoder is enabled and will generate IRQs to
indicate VAD status changes.
1
X Encoder is enabled and will generate periodic
IRQs to indicate whether PCM data is available or
needed when transcoding.
X
1 Encoder is enabled and will generate periodic
IRQs to indicate whether ADM data is available or
needed when transcoding.
Decoder Control
(Bits 3 – 0)
Bit 3
0
1
1
1
1
Bit 2
X
0
1
X
X
Bit 1
X
0
X
1
X
Bit 0
X
0
X
X
1
Decoder Setting
Decoder is disabled and reset.
Decoder is enabled to run without generating IRQs.
Decoder is enabled and will generate IRQs to
indicate VAD status changes.
Decoder is enabled and will generate periodic
IRQs to indicate whether the PCM data is needed
or available when transcoding.
Decoder is enabled and will generate periodic
IRQs to indicate whether the ADM data is needed
or available when transcoding.
DECODER MODE AND SETUP Register ($D0)
Decimation
Rate (by 4/8)
(Bit 15)
The decoder PCM filter functions as an interpolator for the DAC when PCM words
are being received by the decoder and as a decimator when the decoder is receiving
delta modulation. In the case where delta modulation is received, transcoded PCM
values are available in the DECODE LINEAR PCM OUTPUT Register ($D6) at the
decimation rate. When PCM is received the device can be set to transcode to an
ADM stream available in the DECODE ADM OUTPUT Register ($DA) at the
interpolated rate. A logic 1 sets the interpolation (decimation) rate to 4 (1/4th the bit
rate). A logic 0 sets the interpolation (decimation) rate to 8 (1/8th the bit rate).
© 2003 CML Microsystems Plc
25
D/649/2
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