CMX649 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX649' PDF : 50 Pages View PDF
ADM Codec
CMX649
CLK SOURCE CONTROL Register ($73)
Reserved
(Bits 15-14)
Phase Detect
Input Select
(Bit 13)
These bits are reserved and should be set to a logic 0.
0 = PLL locks to external input clock
1 = PLL locks to external input strobe.
(Bit 12)
0 = PLL locks to data edges.
1 = PLL locks to external clock or strobe edges according to Bit 13 value.
Reserved
(Bits 11-8)
PLL Enable
(Bit 7)
These bits are reserved and should be set to a logic 0.
Setting this bit to a logic 1 enables the phase locked loop in the clock recover circuit.
When the PLL is enabled the decoder ADM bit clock adjusts its phase in increments
of 1/32 of the programmed period to minimise noise due to timing jitter. Setting this
bit to a logic 0 free-wheels the post divide by 64 decode clock divider and thus
produces a bit clock which is synchronised to the XTAL/CLK input.
Decode Bit
Clock Select
(Bit 6)
Encode Bit
Clock Select
(Bits 5 – 4)
Setting this bit to a logic 1 selects the bit clock generated by the clock recovery
circuit. Setting this bit to a logic 0 selects a bit clock externally applied to the RX
CLK pin.
These bits allow for the selection of three different sources for the encode bit clock.
Bit 5
X
0
1
Bit 4
0
1
1
Encode Bit Clock
External Tx Clock Pin.
Internally Generated encode clock.
Internally Generated from decode
clock.
Note that a system clock or crystal is always required on the XTAL/CLK pin, in order to generate the
various internal timing signals, even when Rx and Tx Clocks are recovered from the RX DATA pin.
Data Filter
Bypass
(Bit 3)
Data Filter and
Slicer Power
Control
(Bits 2 – 1)
Setting this bit to a logic 1 bypasses the data filter and inputs the RX DATA signal
directly into the data slicer.
These bits are dedicated to power/current control for the data filter and slicer.
Bit 2
0
0
1
1
Bit 1
0
1
0
1
Power Level Setting
Power down (Off).
Lowest power (for bit rates less than 32kbps).
Low power (for bit rates between 32kbps and
64kbps).
Normal operation (for bit rates greater than
64kbps).
When the Data Filter and Slicer are powered off, the RX DATA input pin signal must
conform to logic level amplitudes. When operating the device in buffered I/O modes,
the Data Filter and Slicer should be powered off.
© 2003 CML Microsystems Plc
24
D/649/2
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