CMX649 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX649' PDF : 50 Pages View PDF
ADM Codec
CMX649
Decode Bit
Clock Divider
(Bits 5 – 3)
These bits control the decode bit clock divider.
Bit 5
0
0
0
0
1
1
1
1
Bit 4
0
0
1
1
0
0
1
1
Bit 3
0
1
0
1
0
1
0
1
Divider Ratio
1.000
2.000
2.250
2.625
3.000
3.125
3.375
3.500
Encode Bit
Clock Divider
(Bits 2 – 0)
These bits control the encode bit clock divider.
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
Divider Ratio
1.000
2.000
2.250
2.625
3.000
3.125
3.375
3.500
The audio filter clock divider should be programmed to set the audio filter clock as near as possible to
256kHz, via selection of the XTAL frequency and the Filter Prescaler and Filter Divider settings.
The encoder and decoder ADM bit rate clocks should be programmed to the desired ADM bit rate or PCM
sample rate, multiplied by the interpolation/decimation setting of the PCM filter. The PCM filter can be
programmed to run at either 4x or 8x the PCM sample rate depending on the corresponding setting in the
encode/decode processors.
The encoder and decoder ADM bit rate clocks are further divided by a constant factor of 64 (unless the
PLL is enabled in which case the average is near 64 but can pull off slightly depending on the reference
source).
© 2003 CML Microsystems Plc
23
D/649/2
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