CMX869 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX869' PDF : 46 Pages View PDF
Low Power V.32 bis Modem
CMX869
The Call Progress Detector measures the amplitude of the signal at the output of a 275Hz - 665Hz
bandpass filter and sets bit 10 of the Status Register to 1 when the signal level exceeds the
measurement threshold. The response of the Call Progress filter, including the effect of external
components of figures 4a and 4b, is shown in Figure 6.
10
0
-10
-20
dB
-30
-40
-50
-60
0
0.5
1
1.5
2
2.5
3
3.5
4
kHz
Figure 6 Response of Call Progress Filter
The Answer Tone Detector measures both amplitude and frequency of the received signal and sets bit 6
or bit 7 of the Status Register when a valid 2225Hz or 2100Hz signal is received.
5.7 Rx Modem Filterering and Demodulation
When the receive part of the CMX869 is operating as a modem, the received signal is fed through a
bandpass filter to attenuate unwanted signals. The characteristics of the filter are determined by the
chosen receive modem type and frequency band.
The output of the filter is fed to the appropriate FSK or QAM demodulator depending on the selected
modem type.
In FSK modem modes the signal level at the output of the Filter is also measured, compared to a
threshold value, and the result controls bit 10 of the Status Register.
In QAM modem modes, a V.32 bis/V.32 echo canceller is included, which will work with a round trip delay
of up to 1.25seconds.
5.8 Rx Modem Pattern Detectors
In FSK modem modes the received bit stream is monitored for continuous 1’s, for continuous 0’s, and for
continuous alternating 1’s and 0’s. Bit 7, 8 or 9 of the Status Register will be set to 1 whenever 32 bits of
the appropriate pattern has been received and will then remain at 1 for 12 bit times after the end of the
detected pattern unless the receive operating mode is changed, in which case the pattern detectors are
reset within 2 msec.
In QAM modem modes a V.14 ‘Break’ signal detector is implemented in Start-Stop mode by monitoring
the received data and setting bit 8 of the Status Register when 2N + 4 consecutive 0’s have been
received, N being the total number of bits per character including the Start, Stop and any Parity bits.
The demodulated data is passed through a de-scrambler according to the requirements of the receiver
operating mode. This function is enabled automatically, as required.
© 2003 CML Microsystems Plc
15
D/869/1
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