CMX869 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX869' PDF : 46 Pages View PDF
Low Power V.32 bis Modem
CMX869
HDLC mode
In HDLC mode the CMX869 recognises the start and end of an HDLC Frame by monitoring the received
bit stream for the presence of the flag byte (01111110 binary). The received data and FCS octets within
the Frame are then passed to the C-BUS Rx Data Register (one or two octets at a time depending on the
setting of the Rx Mode Register ’2-character’ bit, b6) after removal of any ‘stuffed’ 0’s. A 16-bit Frame
Check Sequence is calculated from the received data octets and compared to the received FCS at the
end of the Frame, bit 4 of the Status Register being set to 1 if the two FCSs do not match.
If 2-character mode has been selected by setting b6 of the Rx Mode Register to 1, received data and
FCS octets will normally be transferred to the C-BUS Rx Data Register two at a time, and Status Register
bit 1 will be set to 1. However if the message contains an odd number of octets, Status Register bit 1 will
be cleared to 0 when the final octet is transferred to the Rx Data Register, to indicate that the controlling
µC should read only 8 bits from the C-BUS Rx Data Register.
Status Register Rx Data Ready and Rx Data Overflow bits
Whenever a new character or characters is copied into the C-BUS Rx Data Register, the Rx Data Ready
flag bit b6 of the Status Register is set to ‘1’ to prompt the µC to read the new data.
If the µC has not read the previous data from the Rx Data Register by the time that the CMX869 places
fresh data into it, the Rx Data Overflow flag bit, b5 of the Status Register, will be set to 1.
The Rx Data Ready flag and Rx Data Overflow bits are cleared to 0 when the Rx Data Register is read
by the µC.
Overspeed
For QAM (V.22, V.22 bis, V.32 and V.32 bis) Start-Stop modes, V.14 requires that the receive USART be
able to cope with missing Stop bits; up to 1 missing Stop bit in every 8 consecutive received characters
being allowed for the +1% overspeed (basic signalling rate) V.14 mode and 1 in 4 for the +2.3%
overspeed (extended signalling rate) mode.
To accommodate the requirements of V.14, the CMX868 Rx Mode Register can be set for 0, +1% or
+2.3% overspeed operation in QAM modes. Missing Stop bits beyond those allowed by the selected
overspeed option will set the Rx Framing Error flag bit of the Status Register.
© 2003 CML Microsystems Plc
17
D/869/1
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