CS53L32A-KZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS53L32A-KZ' PDF : 38 Pages View PDF
CS53L32A
5. PIN DESCRIPTION
Interface Power
VL 1 20 RST
Reset
Master Clock
MCLK 2 19 VQ
Quiescent Voltage
Serial Clock
SCLK 3 18 AIN_L1 Analog Input 1 Left
Serial Audio Data Out
SDOUT 4 17 AIN_R1 Analog Input 1 Right
Analog Power
VA 5 16 REF_GND Reference Ground
Ground
GND 6 15 AIN_L2 Analog Input 2 Left
Left/Right Clock
LRCK 7
14 AIN_R2 Analog Input 2 Right
AD0/CS/DIV
AD0/CS/DIV 8
13 FILT+
Positive Voltage Reference
SDA/CDIN/DIF SDA/CDIN/DIF 9
12 AFLTL Anti-Aliasing Capacitor
SCL/CCLK/ChSEL SCL/CCLK/ChSEL 10 11 AFLTR Anti-Aliasing Capacitor
Interface Power
Master Clock
Serial Clock
Serial Audio Data Out
Analog Power
Ground
1
VL (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC.
2
MCLK (Input) - The master clock frequency must be either 256x, 384x,
512x, 768x or 1024x the input sample rate in Base Rate Mode (BRM) and
128x, 192x, 256x, 384x the input sample rate in High Rate Mode (HRM).
Table 16 illustrates several standard audio sample rates and the required
master clock frequencies.
3
SCLK (Input/Output) - Clocks the individual bits of the serial data out of the
SDOUT pin. The required relationship between the Left/Right clock, serial
clock and serial data is defined by the DIF2-0 bytes when in Control Port
mode or by the DIF1-0 pins when in Stand-Alone mode.
4
SDOUT (Output) - Two’s complement MSB-first serial data is output on this
pin. The data is clocked out of SDOUT via the serial clock and the channel is
determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the DIF2-0 bytes
when in Control Port mode or by the DIF pin when in Stand-Alone mode.
5
VA (Input) - Analog power supply. Typically 1.8 to 3.3 VDC.
6
GND (Input) - Ground Reference.
MCLK (MHz)
Sample
Rate
(kHz)
128x
HRM
192x
256x*
384x*
256x
384x
BRM
512x
32
4.0960 6.1440 8.1920 12.2880 8.1920 12.2880 16.3840
44.1
5.6448 8.4672 11.2896 16.9344 11.2896 16.9344 22.5792
48
6.1440 9.2160 12.2880 18.4320 12.2880 18.4320 24.5760
64
8.1920 12.2880 16.3840 24.5760
-
-
-
88.2
11.2896 16.9344 22.5792 33.8688
-
-
-
96
12.2880 18.4320 24.5760 36.8640
-
-
-
* MCLKDIV = 1 in Control Port mode or DIV= Hi when in Stand-Alone mode
Table 16. Common Clock Frequencies
768x*
24.5760
32.7680
36.8640
-
-
-
1024x*
32.7680
45.1584
49.1520
-
-
-
26
DS513PP1
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