CS53L32A-KZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS53L32A-KZ' PDF : 38 Pages View PDF
CS53L32A
shown in Figure 7. There is no CS pin. Pin AD0
forms the partial chip address and should be tied to
VL or GND as required. The upper 6 bits of the 7
bit address field must be 001000. To communicate
with the CS53L32A the LSB of the chip address
field, which is the first byte sent to the CS53L32A,
should match the setting of the AD0 pin. The eighth
bit of the address byte is the R/W bit (high for a
read, low for a write). If the operation is a write, the
next byte is the Memory Address Pointer which se-
lects the register to be read or written. See Section
7.3, Memory Address Pointer (MAP). If the opera-
tion is a read, the contents of the register pointed to
by the Memory Address Pointer will be output. Set-
ting the auto increment bit in MAP, allows succes-
sive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
Note: The Two-Wire control port mode is compatible
with the I2C protocol.
7.3 MEMORY ADDRESS POINTER (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
INCR (Auto MAP Increment Enable)
Default = ‘0’.
0 - Disabled
1 - Enabled
MAP0-2 (Memory Address Pointer)
Default = ‘000’.
4
Reserved
0
3
Reserved
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
30
DS513PP1
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