CS53L32A-KZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS53L32A-KZ' PDF : 38 Pages View PDF
CS53L32A
6. APPLICATIONS
6.1 Grounding and Power Supply
Decoupling
As with any high resolution converter, the
CS53L32A requires careful attention to power sup-
ply and grounding arrangements to optimize per-
formance. Figure 5 shows the recommended power
arrangement with VA and VL connected to clean
supplies. Decoupling capacitors should be located
as close to the device package as possible.
6.2 Oversampling Modes
The CS53L32A operates in one of two oversam-
pling modes. Base Rate Mode supports input sam-
ple rates up to 50 kHz while High Rate Mode
supports input sample rates up to 100 kHz. See
Table 16 for more details.
6.3 Recommended Power-up Sequence
1) Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and
VQ will remain low.
2) Bring RST high. The device will remain in a
low power state with VQ low and will initiate
the Stand-Alone power-up sequence. The con-
trol port will be accesable at this time. If con-
trol port operation is desired, write the CP_EN
bit prior to the completion of the Stand-Alone
power-up
sequence,
approximately
1024 LRCK cycles. Writing this bit will halt
the Stand-Alone power-up sequence and ini-
tialize the control port to its default settings.
The desired register settings can be loaded
while keeping the PDN bit set to 1.
3) If Control Port mode is selected via the CP_EN
bit, set the PDN bit to 0 which will initiate the
power-up sequence, which requires approxi-
mately 50 µS.
7. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
The control port has 2 modes: SPI and Two Wire.
If Two Wire operation is desired, AD0/CS should
be tied to VL or GND. If the CS53L32A ever de-
tects a high to low transition on AD0/CS after pow-
er-up, SPI mode will be selected.
7.1 SPI Mode
In SPI mode, CS is the CS53L32A chip select sig-
nal, CCLK is the control port bit clock, CDIN is the
input data line from the microcontroller and the
chip address is 0010000. All signals are inputs and
data is clocked in on the rising edge of CCLK. All
CS53L32A registers are write-only in SPI mode.
Figure 6 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into the register designated by
the MAP.
The CS53L32A has a MAP auto increment capa-
bility, enabled by the INCR bit in the MAP. If
INCR is a zero, then the MAP will stay constant for
successive writes. If INCR is set to a 1, then MAP
will auto increment after each byte is written, al-
lowing block writes of successive registers.
7.2 Two Wire Mode
In Two Wire mode, SDA is a bidirectional data
line. Data is clocked into and out of the part by the
clock, SCL, with the clock to data relationship as
DS513PP1
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