CS53L32A-KZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS53L32A-KZ' PDF : 38 Pages View PDF
CS53L32A
Left/Right Clock
Address Bit
MCLK Divide Enable
Serial Control Data I/O
Digital Interface Format
7
LRCK (Input/Output) - The Left/Right clock determines which channel is cur-
rently being output on the serial audio data line SDOUT. The frequency of
the Left/Right clock must be at the input sample rate. The required relation-
ship between the Left/Right clock, serial clock and serial data is defined by
the DIF2-0 bytes when in Control Port mode or by the DIF pin when in
Stand-Alone mode.
8
AD0/CS (Control Port Mode) (Input) - In Two Wire mode, AD0 is a chip
address bit. CS is used to enable the control port interface in SPI mode.
8
DIV (Stand-Alone Mode) (Input) - When high, the chip will enter High Rate
Mode. When this pin is low, the chip will enter Base Rate Mode.
9
SDA/CDIN (Control Port Mode) (Input/Output) - In Two Wire mode,SDA is
a data I/O line. CDIN is the input data line for the control port interface in SPI
mode.
9
DIF (Stand-Alone Mode) (Input) - The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Digital Interface
Format.
DIF
DESCRIPTION
0
I2S, up to 24-bit data
1
Left Justified, up to 24-bit data
Table 17. Digital Interface Format - DIF
(Stand-Alone Mode)
Serial Control
Interface Clock
Channel Select
10
SCL/CCLK (Control Port Mode) (Input) - Clocks the serial control data into
or from SDA/CDIN/DIF.
10
ChSEL (Stand-Alone Mode) (Input) - The analog data path is determined
by the Channel Select bit. These options are detailed in Table 18.
ChSEL
0
1
DESCRIPTION
Channel 1 directly to A/D
Channel 2 with 32dB of gain
Table 18. Channel Select Options
Anti-Aliasing Capacitors
11, 12
AFLTR, AFLTL (Output) - Anti-aliasing capacitors for the left and right chan-
nels. An external capacitor is required from AFLTR and AFLTL to ground, as
shown in Figure 4. AFLTR and AFLTL are not intended to supply external
current, and any current drawn from these pins will alter device perfor-
mance.
Positive Voltage
Reference
13
FILT+ (Output) - Positive reference for internal sampling circuits. An external
capacitor is required from FILT+ to ground, as shown in Figure 5. The rec-
ommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of
PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has
a typical source impedence of 250 kΩ and any current drawn from this pin
will alter device performance.
Analog Inputs
14, 15, 17, and 18 AIN_R1, AIN_L1, AIN_R2, AIN_L2 (Input) - Channel 1/Channel 2 analog
inputs.
Reference Ground
16
REF_GND (Input) - Ground reference for the internal sampling circuits. Must
be connected to ground.
Quiescent Voltage
19
VQ (Output) - Filter connection for internal A/D converter quiescent refer-
ence voltage. A capacitor must be connected from VQ to ground. VQ is not
intended to supply external current. VQ has a typical source impedence of
250 kΩ and any current drawn from this pin will alter device performance.
DS513PP1
27
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