CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
CS8920A
• bit A, RouteWakeup: Set this bit to route the
wakeup signal to both the presently pro-
grammed interrupt pin and the EWAKE pin.
This bit defaults to clear, meaning the
wakeup signal is routed only to the EWAKE
pin. Note that the interrupt pin is used only if
the CS8920A has determined that the ISA
bus is powered up.
RxEvent (register 4) and ISQ
• bit F, Wakeup frame received: This bit is set
when a valid wakeup frame is received. This
bit is cleared when read. It may be set again
only by a new wakeup frame.
For more information about the status and con-
trol bits, see Section 4.4.1
NORMAL State
While in the NORMAL state, The CS8920A re-
ceives all packets and does not check for wakeup
frames. The CS8920A remains in NORMAL
state until a reset occurs or until the software sets
the WakeupEN bit to 1. The reset causes the
CS8920A to enter the RESET state. Setting
WakeupEN to 1 causes the CS8920A to enter the
STANDBY state.
While in the NORMAL state, and before enter-
ing the STANDBY state, the CS8920A must be
initialized with the following information:
• IA must be loaded into the CS8920A.
• RxCTL (Register 5) must be set for appropri-
ate address filtering set.
• LineCTL (Register 13) bit 7, SerRxOn, must
be set. This turns on the receiver.
• The RouteWakeup bit (LineCTL, bit A) must
be configured.
DS238PP2
• If an interrupt is being used, an Interrupt Pin
must be enabled via BusCTL, register 17, bit
F.
If the CS8920A is to enter the SUSPEND or
STANDBY state from the RESET mode, then
during the NORMAL state, the software must
ensure that the EEPROM initialization section
contains the following:
• WakeupEn bit set to 1 (Reg 13, LineCTL, bit
F).
• Individual Address
• RxCTL (Register 5) must be set for appropri-
ate address filtering set.
• LineCTL (Register 13) bit 7, SerRxOn, must
be set. This turns on the receiver.
• The RouteWakeup bit (LineCTL, bit A) must
be configured.
If the CS8920A enters the STANDBY state from
the RESET state, the driver may select an Inter-
rupt pin via the BusCTL register, bit F after the
reset. Selecting the Interrupt pin via the
EEPROM may interfere with PnP configuration
management.
RESET State
The CS8920A enters the RESET state in re-
sponse to one of the following:
• The ISA bus reset signal is recognized. Note
that if the CS8920A has previously recog-
nized that the ISA bus was powered down,
the CS8920A qualifies a reset request by 15
transitions on MEMR. This qualification fil-
ters spurious signals on the reset pin.
• A reset request is written to bit 6 of register
SelfCTL (register 15).
117
Share Link: 
