CXP973F064 View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
MFG CO.
'CXP973F064' PDF : 42 Pages View PDF
Pin Assignment 3 (Top View) 104-pin LFLGA package
CXP973F064
1
2
3
4
5
6
7
8
9 10 11 12 13
A
97 95 92 90 87 84 82 80 77
PB0 PA6 PA3 PA1 VDD PH6 PH4 PH2 PK6
B
99 96 93 91 88 85 81 76 75
PB2 PA7 PA4 PA2 VSS PH7 PH3 PK5 PK4
C 2 100
98 94 89 86 83 79 78
74 72
PB5 PB3
PB1 PA5 PA0 PWE PH5 PH1 PH0
PK3 PK1
D5
1
3
73 70 69
PC0 PB4 PB6
PK2 AVDD AVREF
E7
6
4
71 68 67
PC2 PC1 PB7
PK0 AVSS PJ7
F 10 9 8
66 65 64
PC5 PC4 PC3
PJ6 PJ5 PJ4
G 12 13 11
63 61 62
PC7 VSS PC6
PJ3 PJ1 PJ2
H 15 16 14
58 60 59
PD1 PD2 PD0
PI6 PJ0 PI7
J 17 18 19
54 56 57
PD3 PD4 PD5
K 20 21 23
PI3 PI4 PI5
53 51 55
PD6 PD7 PE1
PI2 PI0 VSS
L 22 24
28 30 33 36 41 46 48
50 52
PE0 PE2
PE6 PF0 PF3 PF6 EXTAL PG3 PG5
PG7 PI1
M
25 26 32 35 38 40 43 45 49
PE3 PE4 PF2 PF5 RST XTAL PG0 PG2 PG6
N
27 29 31 34 37 39 42 44 47
PE5 PE7 PF1 PF4 PF7 VSS VDD PG1 PG4
Note) 1. PWE (Pin C7) must be connected to NC for Mask ROM.
2. Vss and AVss (Pins B7, E12, G2, K13 and N8) must be connected to GND.
3. VDD and AVDD (Pins A7, D12 and N9) must be connected to VDD.
–5–
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