CXP973F064 View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
MFG CO.
'CXP973F064' PDF : 42 Pages View PDF
CXP973F064
Symbol
I/O
Functions
PH0/SDA
Output / I/O
I2C bus interface data I/O.
PH1/SCL
PH2/RxD
PH3/TxD
PH4/RMC
PH5/TETC
PH6/XWR
Output / I/O
I/O / Input
I/O / Output
I/O / Input
I/O / Input
Output / Output
(Port H)
8-bit port. Lower 2 bits
are for large current
N-ch open drain
outputs; medium 4 bits
are for I/O; upper 2 bits
are for output. Medium
4 bits can be specified
in 1-bit units.
(8 pins)
I2C bus interface clock I/O.
UART reception data input. (common with data
reception during on-board rewrite boot mode)
UART transmission data output. (common with
data transmission during on-board rewrite boot
mode)
Remote control signal input.
On-board rewrite boot mode setting. (Total 3 pins)
External register interface write signal.
PH7/XRD
Output / Output
External register interface read signal.
PI0/SCS2
I/O / Input
Serial chip select (CH2) input.
PI1/SI2
PI2/SO2
PI3/SCK2
PI4/AN0/
KS0
to PI7/AN3/
KS3
I/O / Input
I/O / Output
I/O / I/O
I/O / Input /
Input
PJ0/AN4/
KS4
to PJ7/AN11/
KS11
I/O / Input /
Input
(Port I)
8-bit I/O port. I/O can
be specified in 1-bit
units.
(8 pins)
Serial data (CH2) input.
Serial data (CH2) output.
Serial clock (CH2) I/O.
(Port J)
8-bit I/O port. I/O can
be specified in 1-bit
units.
(8 pins)
Analog input for
A/D converter.
(12 pins)
Standby release input
function can be
specified in 1-bit units.
(12 pins)
PK0 to PK2 I/O
PK3/ADTEN I/O / Input
PK4/ADTRG
PK5/TETB
PK6/TETA
EXTAL
XTAL
RST
I/O / Input
Output / Input
Output / Input
Input
Input
AVDD
AVREF
AVss
VDD
Vss
PWE
Input
Input
(Port K)
7-bit port. Lower 5 bits
are for I/O; upper 2 bits
are for output. Lower
5 bits can be specified
in 1-bit units.
(7 pins)
A/D converter operation enable input by external
trigger.
External trigger input for A/D converter.
On-board rewrite boot mode setting.
(Total 3 pins)
Connects a crystal for main clock oscillation. (When the clock is supplied
externally, input it to EXTAL and input an opposite phase clock to XTAL.)
System reset. Active at "L" level.
Positive power supply for A/D converter. (Must be the same voltage with
VDD.)
Reference voltage input for A/D converter. (Must be the same voltage with
VDD.)
GND for A/D converter.
Positive power supply. (Connect both VDD pins to positive power supply.)
GND (Connect all four Vss pins to GND.)
FLASH EEPROM rewrite enable.
–7–
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