CXP973F064 View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
MFG CO.
'CXP973F064' PDF : 42 Pages View PDF
Pin
PC4/PPO12/
XCS3
to PC7/PPO15/
XCS0
Circuit format
XCS output setting
("0" after a reset)
XCS3 to XCS0
PPO12 to PPO15
1
MPX
0
PC register
("0" after a reset)
PCD register
("0" after a reset)
Internal
data bus
RD
CXP973F064
After a reset
Hi-Z
IP
PD0/D0/KS12
to PD7/D7/
KS19
WR (external register area)
Internal data bus
External register
I/F
External register operation enable
CLR
PD register
("0" after a reset)
CLR
PDD register
("0" after a reset)
Internal data bus
RD
Standby release
Internal data bus
External register
I/F
RD (external register area)
∗
IP
External register operation enable
∗ Large current drive
5mA (VDD = 2.7 to 3.6V)
Hi-Z
PE0/INT0
to PE7/INT7/
CINT
PE register
(Undefined after a reset)
PED register
("0" after a reset)
Internal data bus
RD
INT0 to INT7/CINT
–9–
IP
CMOS Schmitt input
Hi-Z
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