CY8C20110 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CY8C20110' PDF : 46 Pages View PDF
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Errata
CY8C20110
This section discusses the changes between the firmware revisions ×15 and ×1B in CY8C20110 devices. All shipments of samples
and production parts with firmware version ×1B will encounter the following changes from the previous (×15) version of the firmware.
Cypress inventory has been rotated to the ×1B firmware by WW35, and all distributor inventory will be rotated by WW42 of 2008.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
CY8C20110
Package Type
All Packages
Operating Range
Commercial / Industrial
Product Status
The CY8C20110 CapSense Express device has been qualified and is available in production quantities. From now on, customers are
requested to use production release of CY8C20110 with x1B firmware version.
CapSense Express CY8C20110 Errata Summary
The following table defines the errata applicable to CY8C20110 device.
Table 19. CapSense Express CY8C20110 Errata Summary
Item Issues/Changes
1
I2C ACK
Description
Reduction of I2C ACK timing response by the
CapSense Express slave.
Time in Normal Operating Mode.
Fix Status
Worst case Ack timing of 140 µs for all critical
registers (Input, Output, CapSense™ Global
Parameters, CapSense Buttons/Slider Read-back
Values). For more information on critical registers
I2C timings, refer to application note AN44208
“CapSense Express - I2C Communication Timing
Analysis”.
2
I2C ACK
Reduction of I2C ACK timing response by the
CapSense Express slave.
Time when executing commands to store
configuration in Flash.
The CY8C20110 device ACK to host within
100 µs, but is not accessible for any other
operation until configuration is successfully stored
into flash memory and the device is ready to
execute the next command. For more information
on I2C timings, refer to Application Note AN44208
“CapSense Express - I2C Communication Timing
Analysis”.
3
Data Filtering
Addition of two on-chip filtering algorithms for im- Averaging Filter
proved CapSense performance and better noise
immunity.
This smoothens the raw count data, and results in
better noise immunity and performance. The filter
can average 2, 4, 8, or 16 samples.
Drop the Sample Filter
This discards any acquired CapSense sample if an
I2C communication occurs after the scan process
has already started.
For more information on filtering, refer to
application note AN48430 “CapSense Express
-Noise Filtering Methods”.
4
PWM Control
The PWM output functionality has been added on Four configuration registers (18h, 19h, 1Ah, 1Bh)
GPIOs to support LED brightness control.
are added to set PWM duty cycles and modes.
This set of registers provides options that support
15 duty cycles on PWM output and 4 modes of
PWM operations, which are defined as Normal,
Single Pulse, Delayed Transition, and Toggle
Flip-Flop. For more information on duty cycles and
PWM mode settings, refer to application note
AN47716 “Configuring PWM for LED Intensity
Control”.
Document Number: 001-54606 Rev. *J
Page 41 of 46
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