DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
puts, Direction Registers, and port pin input are all
connected to the Port Data Buffer (PDB).
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in PSDsoft ExpressTM, then the Direction Register
has sole control of the buffer that drives the port
pin.
The contents of these registers can be altered by
the DSP. The Port Data Buffer (PDB) feedback
path allows the DSP to check the contents of the
registers.
Ports B, and C have embedded IMCs. The IMCs
can be configured as registers (for sampling or de-
bouncing), as transparent latches, or direct inputs
to the PLDs. The registers and latches are clocked
by a product term from the PLD AND Array. The
outputs from the IMCs drive the PLD input bus and
can be read by the DSP. See the section entitled
“Input Macrocell”, on page 31.
Port Operating Modes
The I/O Ports have several modes of operation.
Modes are defined using PSDsoft ExpressTM, and
then runtime control from the DSP can occur using
the registers in the csiop block. See Application
Note AN1171 for more detail.
Table 11 summarizes which modes are available
on each port. Each of the port operating modes
are described in the following sections.
Table 11. Port Operating Modes
) Port Mode
Port B
t(s MCU I/O
Yes
uc PLD I/O
d McellAB Outputs
Yes
ro McellBC Outputs
Yes
Additional Ext. CS Outputs
No
P PLD Inputs
Yes
te JTAG ISP
No
le Note: 1. Can be multiplexed with other I/O functions.
so MCU I/O Mode. In the MCU I/O mode, the DSP
b uses the I/O Ports block to expand its own I/O
O ports. The DSP can read I/O pins, set the direction
- of I/O pins, and change the state of I/O pins by ac-
) cessing the registers in the csiop block. The csiop
t(s register definition and their addresses may be
found in Table 4.
uc The MCU I/O direction may be changed by writing
d to the corresponding bit in the Direction Register,
ro or by the output enable product term. When the pin
is configured as an output, the content of the Data
P Out Register drives the pin. When configured as
te an input, the DSP can read the port input through
the Data In buffer. See Figure 19.
le PLD I/O Mode. Inputs from Ports B and C to ei-
so ther PLD (DPLD or CPLD) come through IMCs. In-
bputs from Port D to either PLDs are routed directly
Oin and do not use IMCs. Outputs from the CPLD to
Port C
Yes
Port D
Yes
No
No
Yes
No
No
Yes
Yes
Yes
Yes1
No
PLD, or by resetting the corresponding bit in the
Direction Register to 0. The corresponding bit in
the Direction Register must not be set to logic 1 by
the DSP if the pin is defined for a PLD input signal
in PSDsoft Express. The PLD I/O mode is defined
in PSDsoft Express by specifying PLD equations.
JTAG In-System Programming (ISP). Some of
the pins on Port C are based on the IEEE 1194.1
JTAG specification and is used for In-System Pro-
gramming (ISP). You can multiplex the function of
these Port C JTAG pins with other functions. ISP
is not performed very frequently in the life of the
product, so multiplexing these pin’s functions with
general purpose I/O functions gives more utility
from Port C. See the section entitled “Program-
ming In-Circuit Using JTAG ISP”, and Application
Note AN1153.
Port Configuration Registers (PCR). Each Port
Port B come from the OMC group MCELLAB0-7. has a set of Port Configuration Registers (PCR)
Outputs from the CPLD to Port C come from OMC used for configuration of the pins. The contents of
group MCELLBC0-7. Outputs from the DPLD to the registers can be accessed by the DSP through
Port D come from the external chip select logic normal read/write bus cycles of the csiop registers
block ECS0-2.
listed in Table 4.
All PLD outputs may be tri-stated at the Port pins
with a control signal. This output enable control
signal can be defined by a product term from the
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
33/63
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