DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
port. The three Port Configuration Registers
(PCR), are shown in Table 12. Default is logic 0.
Table 14. Port Pin Direction Control, Output
Enable P.T. Defined
Table 12. Port Configuration Registers (PCR)
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
Register Name
Port
DSP Access
0
0
Input
Data In
B,C,D
Read
0
1
Output
Data Out
B,C,D
Write/Read
1
0
Output
Direction
B,C,D
Write/Read
1
1
Output
Drive Select1
B,C,D
Write/Read
Note: 1. See Table 16 for Drive Register bit definition.
Table 15. Port Direction Assignment Example
Data In Register. The DSP may read the Data In
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
registers in the csiop block at any time to deter-
mine the logic state of a Port pin. This will be the
0
0
0
0
0
1
1
1
state at the pin regardless of whether it is driven by Figure 20 and Figure 21 show the Port Architec-
a source external to the DSM or driven internally ture diagrams for Ports B and C, respectively. The
from the DSM device. Reading a logic zero for a bit
) in a Data In register means the corresponding Port
t(s pin is also at logic zero. Reading logic one means
the pin is logic one. Each bit in a Data In register
c corresponds to an individual Port pin. For a given
u Port, bit 0 in a Data In register corresponds to pin
d 0 of the Port. Example, bit 0 of the Data In register
ro for Port B corresponds to Port B pin PB0.
P Data Out Register. The DSP may write (or read)
te the Data Out register in the csiop block at any
time. Writing the Data Out register will change the
le logic state of a Port pin only if it is not driven or
o controlled by the CPLD. Writing a logic zero to a bit
s in a Data Out register will force the corresponding
b Port pin to be logic zero. Writing logic one will drive
O the pin to logic one. Each bit in the Data Out reg-
- isters correspond to Port pins the same way as the
) Data In registers described above. When some
t(s pins of a Port are driven by the CPLD, writing to
the corresponding bit in a Data Out register will
uc have no effect as the CPLD overrides the Data Out
d register.
ro Direction Register. The Direction Register, in
conjunction with the output enable (except for Port
P D), controls the direction of data flow in the I/O
te Ports. Any bit set to 1 in the Direction Register
le causes the corresponding pin to be an output, and
any bit set to 0 causes it to be an input. The default
so mode for all port pins is input.
ObTable 13. Port Pin Direction Control, Output
direction of data flow for Ports B, and C are con-
trolled not only by the direction register, but also by
the output enable product term from the PLD AND
Array. If the output enable product term is not ac-
tive, the Direction Register has sole control of a
given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 15. Since
Port D only contains three pins (shown in Figure
23), the Direction Register for Port D has only the
three least significant bits active.
Drive Select Register. The Drive Select Register
configures the pin driver as Open Drain or CMOS
(standard push/pull) for some port pins, and con-
trols the slew rate for the other port pins. An exter-
nal pull-up resistor should be used for pins
configured as Open Drain. Open Drain outputs are
diode clamped, thus the maximum voltage on an
pin configured as Open Drain is Vcc + 0.7V.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
Note that the slew rate is a measurement of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to 1. The default rate is standard slew.
Table 16 shows the Drive Register for Ports B, C,
and D. It summarizes which pins can be config-
Enable P.T. Not Defined
ured as Open Drain outputs and which pins the
Direction Register Bit
Port Pin Mode
slew rate can be set for.
0
Input
1
Output
34/63
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