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DSM2180F3 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'DSM2180F3' PDF : 63 Pages View PDF
Figure 22. Port D Structure
DSM2180F3
DATA OUT
REG.
DQ
WR
ECS[ 2:0]
READ MUX
P
D
B
DATA OUT
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
PORT D PIN
DIR REG.
) D Q
t(s WR
ENABLE PRODUCT
TERM (.OE)
CPLD - INPUT
AI02889
roduc Port D – Functionality and Structure
P Port D has three I/O pins. See Figure 22 and Fig-
te ure 23. Port D can be configured to perform one or
more of the following functions:
le MCU I/O Mode
so DPLD Output – External Chip Selects, ECS0-2
b does not consume OMCs
O CPLD Input – direct input to the CPLD, does not
- use IMCs
t(s) Slew rate – pins can be set up for fast slew rate
c Port D pins can be configured in PSDsoft as in-
u put pins for other dedicated functions:
Obsolete Prod CLKIN (PD1) as input to the OMCs Flip-flops
PSD Chip Select Input (CSI, PD2). Driving this
signal logic High disables the Flash memory,
putting it in standby mode.
External Chip Select. The DPLD also provides
three External Chip Select outputs (ESC0-2) on
Port D pins that can be used to select external de-
vices as defined in PSDsoft Express. Each Exter-
nal Chip Select consists of one product term that
can be configured active High or Low. The output
enable of the pin is controlled by either the output
enable product term or the Direction Register.
(See Figure 23.) External Chip Selects for Port D
pins do not consume OMCs. External chip select
outputs can also come from the CPLD if chip se-
lect equations are specified in PSDsoft Express for
Ports B or C.
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