DSP56300FM View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

DSP56300FM

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

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Serial Host Interface SPI Protocol Timing

RAS

CAS

157

162

163

162

190

170

165

189

177

WR

AA0478

Figure 3-17 DRAM Refresh Access

3.11 Serial Host Interface SPI Protocol Timing

Table 3-17 Serial Host Interface SPI Protocol Timing

No.

Characteristics

Mode

Filter

Mode

Expression

Min Max Unit

140 Tolerable spike width on clock or data in

— Bypassed

—

—

0

ns

Narrow

—

—

50

ns

Wide

—

—

100 ns

141 Minimum serial clock cycle = tSPICC(min)

142 Serial clock high period

Master Bypassed

6×TC+46

106

—

ns

Narrow

6×TC+152

212

—

ns

Wide

6×TC+223

283

—

ns

Master Bypassed 0.5×tSPICC –10

43

—

ns

Narrow

0.5×tSPICC –10

96

—

ns

Wide

0.5×tSPICC –10

131

—

ns

Slave Bypassed

2.5×TC+12

37

—

ns

Narrow

2.5×TC+102

127

—

ns

Wide

2.5×TC+189

214

—

ns

Freescale Semiconductor

DSP56364 Technical Data, Rev. 4.1

3-37

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