DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
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'DSP56300FM' PDF : 148 Pages View PDF
Serial Host Interface (SHI) I2C Protocol Timing
3.12 Serial Host Interface (SHI) I2C Protocol Timing
Table 3-18 SHI I2C Protocol Timing
Standard I2C1
No.
Characteristics
Symbol/
Expression
Standard-Mode
Min Max
Fast-Mode
Unit
Min
Max
Tolerable spike width on SCL or SDA
—
• Filters bypassed
—
0
—
0
ns
• Narrow filters enabled
—
50
—
50 ns
• Wide filters enabled
—
100
—
100 ns
171 SCL clock frequency
172 Bus free time
173 Start condition set-up time
174 Start condition hold time
175 SCL low period
176 SCL high period
177 SCL and SDA rise time
178 SCL and SDA fall time
179 Data set-up time
180 Data hold time
181 Stop condition set-up time
182 Capacitive load for each line
183 DSP clock frequency
• Filters bypassed
FSCL
TBUF
TSU;STA
THD;STA
TLOW
THIGH
TR
TF
TSU;DAT
THD;DAT
TSU;STO
Cb
FDSP
—
100
4.7
—
4.7
—
4.0
—
4.7
—
4.0
—
—
1000
—
300
250
—
0.0
—
4.0
—
—
400
—
1.3
0.6
0.6
1.3
1.3
20 + 0.1 × Cb
20 + 0.1 × Cb
100
0.0
0.6
—
400 kHz
—
μs
—
μs
—
μs
—
μs
—
μs
300 ns
300 ns
—
ns
0.9 μs
—
μs
400 pF
10.6
—
28.5
— MHz
• Narrow filters enabled
11.8
—
39.7
— MHz
• Wide filters enabled
13.1
—
61.0
— MHz
184 HREQ in deassertion to last SCL edge
(HREQ in set-up time)
tSU;RQI
0.0
—
0.0
—
ns
3-44
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
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