DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
Serial Host Interface SPI Protocol Timing
Table 3-17 Serial Host Interface SPI Protocol Timing (continued)
No.
Characteristics
Mode
Filter
Mode
Expression
Min
143 Serial clock low period
144 Serial clock rise/fall time
Master Bypassed 0.5×tSPICC –10
43
Narrow
0.5×tSPICC –10
96
Wide
0.5×tSPICC –10
131
Slave Bypassed
2.5×TC+12
37
Narrow
2.5×TC+102
127
Wide
2.5×TC+189
214
Master
—
—
—
Slave
—
—
—
146 SS assertion to first SCK edge
CPHA = 0
Slave Bypassed
3.5×TC+15
50
Narrow
0
0
Wide
0
0
CPHA = 1
Slave Bypassed
10
10
Narrow
0
0
Wide
0
0
147 Last SCK edge to SS not asserted
Slave Bypassed
12
12
Narrow
102
102
Wide
189
189
148 Data input valid to SCK edge (data input set-up Master/ Bypassed
0
0
time)
Slave
Narrow MAX{(20-TC), 0} 10
Wide
MAX{(40-TC), 0} 30
149 SCK last sampling edge to data input not valid Master/ Bypassed
2.5×TC+10
35
Slave
Narrow
2.5×TC+30
55
Wide
2.5×TC+50
75
150 SS assertion to data out active
Slave
—
2
2
151 SS deassertion to data high impedance
Slave
—
9
—
Max Unit
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
10
ns
2000 ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
9
ns
3-38
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
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