DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
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MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
Serial Host Interface (SHI) I2C Protocol Timing
Table 3-18 SHI I2C Protocol Timing (continued)
Standard I2C1
No.
Characteristics
Symbol/
Expression
Standard-Mode
Min Max
Fast-Mode
Unit
Min
Max
186 First SCL sampling edge to HREQ output
TNG;RQO
ns
deassertion
• Filters bypassed
• Narrow filters enabled
• Wide filters enabled
2 × TC + 30
—
50
—
50
ns
2 × TC + 120
—
140
—
140 ns
2 × TC + 208
—
228
—
228 ns
187 Last SCL edge to HREQ output not
TAS;RQO
ns
deasserted
• Filters bypassed
• Narrow filters enabled
• Wide filters enabled
2 × TC + 30
50
—
50
—
ns
2 × TC + 80
100
—
100
—
ns
2 × TC + 135
155
—
155
—
ns
188 HREQ in assertion to first SCL edge
TAS;RQI
ns
• Filters bypassed
0.5 × TI2CCP -
0.5 × TC - 21
4327
—
927
—
ns
• Narrow filters enabled
4282
—
882
—
ns
• Wide filters enabled
1 RP (min) = 1.5 k¾
4238
—
838
—
ns
3.12.1 Programming the Serial Clock
The programmed serial clock cycle, TI2CCP, is specified by the value of the HDM[5:0] and HRS bits of the
HCKR (SHI clock control register).
The expression for TI2CCP is
where
TI2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1 )]
HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is
operational. When HRS is set, the prescaler is bypassed.
HDM[7:0] are the divider modulus select bits.
A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-45
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