DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
Serial Host Interface (SHI) I2C Protocol Timing
In I2C mode, the user may select a value for the programmed serial clock cycle from
6 × TC(if HDMS[5:0] = $02 and HRS = 1)
to
4096 × TC(if HDMS[7:0] = $FF and HRS = 0)
The programmed serial clock cycle (TI2CCP), SCL rise time (TR), and the filters selected should be chosen
in order to achieve the desired SCL frequency, as shown in Table 3-19.
Table 3-19 SCL Serial Clock Cycle Generated as Master
Filters bypassed
Narrow filters enabled
Wide filters enabled
TI2CCP + 2.5 × TC + 45ns + TR
TI2CCP + 2.5 × TC + 135ns + TR
TI2CCP + 2.5 × TC + 223ns + TR
EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard-mode I2C environment
(FSCL = 100 KHz (i.e. TSCL = 10μs), TR = 1000ns), with filters bypassed
TI2CCP = 10μs – 2.5 × 10ns – 45ns – 1000ns = 893ns
Choosing HRS = 0 gives
HDM[7:0] = (8930ns) ⁄ (2 × 10ns × 8) – 1 = 55.8
Thus the HDM[7:0] value should be programmed to $38 (=56).
171
173
176
175
SCL
177
178
180
172
179
SDA Stop Start
MSB
LSB
174
186
182
189
184
188
HREQ
Figure 3-22 I2C Timing
ACK
Stop
183
187
AA0275
3-46
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
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