DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
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Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
Enhanced Serial Audio Interface Timing
Table 3-20 Enhanced Serial Audio Interface Timing (continued)
No.
Characteristics1, 2, 3
Symbol
Expression
Min Max Condition4 Unit
459 FST input (wl) to transmitter #0 drive enable
—
assertion
—
— 31.0
—
ns
460 FST input (wl) setup time before TXC falling
—
edge
—
2.0
—
x ck
ns
21.0 —
i ck
461 FST input hold time after TXC falling edge
—
—
4.0
—
x ck
ns
0.0
—
i ck
462 Flag output valid after TXC rising edge
—
—
— 32.0
x ck
ns
— 18.0
i ck
463 HCKR/HCKT clock cycle
—
—
40.0 —
ns
464 HCKT input rising edge to TXC output
—
—
— 27.5
ns
465 HCKR input rising edge to RXC output
—
—
— 27.5
ns
1 VCC = 3.16 V ± 0.16 V; TJ = 0°C to +105°C, CL = 50 pF.
2 i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks)
i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock)
3 bl = bit length
wl = word length
wr = word length relative
4 TXC (SCKT pin) = transmit clock
RXC (SCKR pin) = receive clock
FST (FST pin) = transmit frame sync
FSR (FSR pin) = receive frame sync
HCKT (HCKT pin) = transmit high speed clock
HCKR (HCKR pin) = receive high speed clock
5 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
6 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one
before last bit clock of the first word in frame.
7 Periodically sampled and not 100% tested
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-49
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