JTAG Timing
Table 3-22 JTAG Timing1. 2 (continued)
No.
Characteristics
All Frequencies
Unit
Min
Max
509 TMS, TDI data hold time
25.0
—
ns
510 TCK low to TDO data valid
0.0
44.0
ns
511 TCK low to TDO high impedance
0.0
44.0
ns
1 VCC = 3.3 V ± 0.16 V; TJ = 0°C to +105°C, CL = 50 pF
2 All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
TCK
(Input)
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Data
Outputs
VIH
503
502
VM
VIL
501
502
VM
503
Figure 3-28 Test Clock Input Timing Diagram
VIL
506
507
VIH
504
505
Input Data Valid
Output Data Valid
506
Output Data Valid
Figure 3-29 Boundary Scan (JTAG) Timing Diagram
AA0496
AA0497
3-54
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor