DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
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Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
Enhanced Serial Audio Interface Timing
3.13 Enhanced Serial Audio Interface Timing
Table 3-20 Enhanced Serial Audio Interface Timing
No.
Characteristics1, 2, 3
Symbol
Expression
Min
430 Clock cycle5
tSSICC
4 × TC
40.0
3 × TC
30.0
TXC:max[3*tc; t454] 40.0
Max Condition4 Unit
—
i ck
ns
—
x ck
—
x ck
431 Clock high period
• For internal clock
• For external clock
432 Clock low period
• For internal clock
• For external clock
433 RXC rising edge to FSR out (bl) high
ns
—
2 × TC − 10.0
10.0 —
1.5 × TC
15.0 —
ns
—
2 × TC − 10.0
10.0 —
1.5 × TC
15.0 —
—
—
— 37.0
x ck
ns
— 22.0
i ck a
434 RXC rising edge to FSR out (bl) low
—
435 RXC rising edge to FSR out (wr) high6
—
436 RXC rising edge to FSR out (wr) low6
—
—
— 37.0
x ck
ns
— 22.0
i ck a
—
— 39.0
x ck
ns
— 24.0
i ck a
—
— 39.0
x ck
ns
— 24.0
i ck a
437 RXC rising edge to FSR out (wl) high
—
—
— 36.0
x ck
ns
— 21.0
i ck a
438 RXC rising edge to FSR out (wl) low
—
—
— 37.0
x ck
ns
— 22.0
i ck a
439 Data in setup time before RXC (SCK in
—
synchronous mode) falling edge
—
0.0
—
x ck
ns
19.0 —
i ck
440 Data in hold time after RXC falling edge
—
—
5.0
—
x ck
ns
3.0
—
i ck
441 FSR input (bl, wr) high before RXC falling
—
edge6
—
23.0 —
x ck
ns
1.0
—
i ck a
442 FSR input (wl) high before RXC falling edge
—
—
1.0
—
x ck
ns
23.0 —
i ck a
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-47
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