DSP56F802 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56F802' PDF : 40 Pages View PDF
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tme
Tnvh1
Trcv
Figure 3-6 Flash Mass Erase Cycle
3.5 Clock Operation
The 56F802 device clock is derived from an on-chip relaxation oscillator. The internal PLL generates a
master reference frequency that determines the speed at which chip operations occur.
The PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2) must be set to 0 for internal
oscillator use.
3.5.1 Use of On-Chip Relaxation Oscillator
The 56F802 internal relaxation oscillator provides the chip clock without the need for an external crystal
or ceramic resonator. The frequency output of this internal oscillator can be corrected by adjusting the 8-bit
IOSCTL (internal oscillator control) register. Each bit added or deleted changes the output frequency of
the oscillator allowing incremental adjustment until the desired frequency is achieved. Figures 9 and 10
show the typical characteristics of the 56F802 relaxation oscillator with respect to temperature and trim
value.
During factory production test, an oscillator calibration procedure is executed which determines an
optimum trim value for a given device (8MHz at 25oC). This optimum trim value is then stored at address
$103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence
(executed after power-up and RESET). This trim routine automatically sets the oscillator frequency by
programming the IOSCTL register with the optimum trim value.
56F802 Technical Data, Rev. 9
22
Freescale Semiconductor
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