DSP56F802 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56F802' PDF : 40 Pages View PDF
11
10
9
8
7
6
5
0 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
Figure 3-8 Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC
3.5.2 Phase Locked Loop Timing
Table 3-9 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency for the PLL1
fosc
4
8
10
MHz
PLL output frequency2
fout/2
40
—
803
MHz
PLL stabilization time4 0o to +85oC
tplls
—
10
—
ms
PLL stabilization time4 -40o to 0oC
tplls
—
100
200
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. Will not exceed 60MHz for the DSP56F802TA60 device.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
56F802 Technical Data, Rev. 9
24
Freescale Semiconductor
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