VIH
TCK
(Input)
VM = VIL + (VIH – VIL)/2
tCY
tPW
VM
VIL
tPW
VM
Figure 3-14 Test Clock Input Timing Diagram
TCK
(Input)
TDI
TMS
(Input)
TDO
(Output)
TDO
(Output)
TDO
(Output)
tDS
tDH
Input Data Valid
tDV
Output Data Valid
tTS
tDV
Output Data Valid
Figure 3-15 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 3-16 TRST Timing Diagram
56F802 Technical Data, Rev. 9
30
Freescale Semiconductor