DSP56F802 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56F802' PDF : 40 Pages View PDF
3.7 Quad Timer Timing
Table 3-11 Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
Timer input period
PIN
4T+6
Timer input high/low period
PINHL
2T+3
Timer output period
POUT
2T
Timer output high/low period
POUTHL
1T
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5 ns.
2. Parameters listed are guaranteed by design.
—
ns
—
ns
—
ns
—
ns
Timer Inputs
PIN
PINHL
PINHL
Timer Outputs
POUT
POUTHL
POUTHL
Figure 3-10 Timer Timing
56F802 Technical Data, Rev. 9
26
Freescale Semiconductor
Share Link: 
