DZPD6710VCB View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'DZPD6710VCB' PDF : 138 Pages View PDF
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 0 — Battery Dead Or Status Change
0
A transition (from high to low for memory card support or either high to low or low to high for I/O
card support) on the BVD1/-STSCHG pin has not occurred since this register was last read.
1
A transition on the BVD1/-STSCHG pin has occurred.
When the socket is configured for memory card support, this bit is set to ‘1’ when a BVD1 battery
dead high-to-low transition has been detected. When the socket is configured for I/O card support,
this bit is set to ‘1’ when the BVD1/-STSCHG pin (see Table 2 on page 20) changes from either
high to low or low to high. This bit is reset to ‘0’ whenever this register is read. In I/O Card
Interface mode, function of this bit is not affected by bit 7 of the Interrupt and General Control
register.
Bit 1 — Battery Warning Change
0
A transition (from high to low) on the BVD2 pin has not occurred since this register was last
read.
1
A transition on the BVD2 pin has occurred.
When a socket is configured for memory card support, this bit is set to ‘1’ when a high-to-low
transition on BVD2 occurs indicating a battery warning was detected. This bit should be ignored
when the socket is configured for I/O card support. This bit is reset to ‘0’ whenever this register is
read.
Bit 2 — Ready Change
0
A transition on the RDY/-IREQ pin has not occurred since this register was last read.
1
A transition on the RDY/-IREQ pin has occurred.
When this bit is ‘1’, a change has occurred in the card RDY/-IREQ pin (see Table 2 on page 20).
This bit will always read 0 when the card is configured as an I/O card. This bit is reset to ‘0’
whenever this register is read.
Bit 3 — Card Detect Change
0
A transition on the -CD1 or -CD2 pins has not occurred since this register was last read.
1
A transition on the -CD1 or -CD2 pins has occurred.
When this bit is ‘1’, a change has occurred on the -CD1 or -CD2 pins (see Table 2 on page 20).
This bit is reset to ‘0’ whenever this register is read.
Datasheet
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