DZPD6710VCB View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'DZPD6710VCB' PDF : 138 Pages View PDF
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
8.0
I/O Window Mapping Registers
The I/O windows must never include 3E0h and 3E1h.
8.1
I/O Window Control
Register Name: I/O Window Control
Index: 07h
Bit 7
Bit 6
Bit 5
Bit 4
Timing
Register
Select 1
Compatibility Auto-Size I/O I/O Window 1
Bit
Window 1
Size
RW:0
RW:0
RW:0
RW:0
Bit 3
Timing
Register
Select 0
RW:0
Bit 2
Register Per: socket
Register Compatibility Type: 365
Bit 1
Bit 0
Compatibility Auto-Size I/O I/O Window 0
Bit
Window 0
Size
RW:0
RW:0
RW:0
Bit 0 — I/O Window 0 Size
0
8-bit data path to I/O Window 0.
1
16-bit data path to I/O Window 0.
When bit 1 below is ‘0’, this bit determines the size of the data path to I/O Window 0. When bit 1 is
‘1’, this bit is ignored.
Bit 1 — Auto-Size I/O Window 0
0
I/O Window 0 Size (see bit 0 above) determines the data path to I/O Window 0.
1
The data path to I/O Window 0 will be determined based on -IOIS16 returned by the card.
This bit determines the data path to I/O Window 0. Note that when this bit is ‘1’, the -IOIS16 signal
(see Table 2 on page 20) determines the width of the data path to the card.
Bit 3 — Timing Register Select 0
0
Accesses made with timing specified in Timing Set 0.
1
Accesses made with timing specified in Timing Set 1.
This bit determines the access timing specification for I/O Window 0 (see “Setup Timing 0–1” on
page 84).
58
Datasheet
Share Link: 
