DZPD6710VCB View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'DZPD6710VCB' PDF : 138 Pages View PDF
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
8.2
Bit 4 — I/O Window 1 Size
0
8-bit data path to I/O Window 1.
1
16-bit data path to I/O Window 1.
When bit 5 below is ‘0’, this bit determines the size of the data path to I/O Window 1. When bit 5 is
‘1’, this bit is ignored.
Bit 5 — Auto-Size I/O Window 1
0
I/O Window 1 Size (see bit 4) determines the data path to I/O Window 1.
1
The data path to I/O Window 1 will be determined based on -IOIS16 returned by the card.
This bit determines the width of the data path to I/O Window 1. Note that when this bit is ‘1’, the
-IOIS16 signal (see Table 2 on page 20) determines the window size. This bit must be set for
proper ATA mode operation (see “ATA Mode Operation” on page 88).
Bit 7 — Timing Register Select 1
0
Accesses made with timing specified in Timing Set 0.
1
Accesses made with timing specified in Timing Set 1.
This bit determines the access timing specification for I/O Window 1 (see “Setup Timing 0–1” on
page 84).
System I/O Map 0–1 Start Address Low
Register Name: System I/O Map 0–1 Start Address Low
Index: 08h, 0Ch
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Register Per: socket
Register Compatibility Type: 365
Bit 1
Bit 0
Start Address 7:0
RW:00000000
There are two separate System I/O Map Start Address Low registers, each with identical fields.
These registers are located at the following indexes:
Index System I/O Map Start Address Low
8h
System I/O Map 0 Start Address Low
Ch System I/O Map 1 Start Address Low
Datasheet
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