EDI9LC644V2012BC View Datasheet(PDF) - White Electronic Designs Corporation
Part Name
Description
MFG CO.
'EDI9LC644V2012BC' PDF : 25 Pages View PDF
FIG. 16
SDRAM MODE REGISTER SET CYCLE
EDI9LC644V
SDRAM AUTO REFRESH CYCLE
HIGH
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
MODE REGISTER SET CYCLE
1. SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS activation.
7. Please refer to Mode Register Set table.
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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