EM78862B
8-Bit RISC Type Microprocessor
6.3 TCC/WDT Pre-Scaler
An 8-bit counter is available as pre-scaler for the TCC or WDT. The pre-scaler is available
only to either the TCC or WDT at a time.
An 8-bit counter is available for TCC or WDT as determined by the status of Bit 3 (PAB) of
CONT register.
The pre-scaler ratio is described in Section 6.2.2 CONT (Control Register).
The TCC/WDT circuit diagram is shown in Fig. 9 below.
Both TCC and pre-scaler are cleared by instructions.
The pre-scaler will be cleared by the WDTC and SLEP instructions when running in WDT
mode.
However, pre-scaler will not be cleared by SLEP instruction when running in TCC mode.
CLK(=Fosc/2)
Data Bus
16.38KHz
or RC/2
OSCSEL
WDT
WDTE
0
1
SYNC
2 Cycles
TCC(R1)
1
0
TS
0
1
PAB
8-BIT Counter
TCC Overflow
Interrupt
PAB
8-to-1 MUX
0
1
MUX
PSR0~PSR2
PAB
WDT Timeout
Fig. 9 TCC WDT Block Diagram
This specification is subject to change without further notice.
Mar.01.2005 (V1.1)19 of 36