EM78862B
8-Bit RISC Type Microprocessor
6.6 Oscillator
The oscillator system is used to generate the device clock. The oscillator system is
composed of an RC or crystal oscillator and a PLL oscillator as shown in the diagram below.
NOTE: Under RC oscillator mode, the pull-up resistor that connects to OSCI pin and OSC0 pin should
be floating.
Under 32768Hz crystal oscillator mode, the crystal is connected between OSCI pin and OSCO
pin. A 20~30pF capacitor should be connected between each of the pins and ground.
In Crystal mode, if the RA (Bit 6)=1, the system clock frequency can be tuned to 3.579MHz.
The initial value of OSCSEL bit is fixed at ‘1’ (crystal oscillator).
Fig. 11 Oscillator and PLL Function Block.
6.7 Interrupt
The EM78862B IC has two types internal interrupts which are falling edge triggered:
TCC timer overflow interrupt (internal)
Two 8-bit counters overflow interrupt
If these interrupt sources change signal from high to low, the RF register will generate '1' flag
to corresponding register if IOCF register is enabled.
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the
interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI
instruction. When one of the interrupts (when enabled) is generated, it will cause the next
instruction to be fetched from address 008H. Once in the interrupt service routine, the source
of the interrupt can be determined by polling the flag bits in the RF register.
NOTE
The interrupt flag bit must be cleared in software before leaving the interrupt
service routine in order to prevent and avoid recursive interrupts.
There are four external interrupt pins, i.e., INT0, INT1, INT2, & INT3, and three internal
interrupts available:
External interrupt signals (INT0, INT1, INT2, and INT3) are from Port 7 Bit 0 to Bit 3. If
IOCF is enabled, then these signals will activate interrupt. Otherwise, these signals will be
treated as general input data.
Internal signals include TCC, CNT1, and CNT2.
22 of 36 Mar.01.2005 (V1.1)
This specification is subject to change without further notice.