EM78862C
8-Bit RISC Type Microprocessor
1. This instruction is applicable to IOC5 ~ IOC9, IOCA, IOCB, IOCC, IOCD, IOCE, &
IOCF only.
2 Source and destination must be the same.
BINARY
INSTRUCTION
HEX
MNEMONIC
OPERATION
0 0110 01rr rrrr
06rr
0 0110 10rr rrrr
06rr
0 0110 11rr rrrr
06rr
0 0111 00rr rrrr
07rr
0 0111 01rr rrrr
07rr
RRC R
RLCA R
RLC R
SWAPA R
SWAP R
R(n) ( R(n-1),
R(0) ( C, C ( R(7)
R(n) ( A(n+1),
R(7) ( C, C ( A(0)
R(n) ( R(n+1),
R(7) ( C, C ( R(0)
R(0-3) → ( A(4-7),
R(4-7) → ( A(0-3)
R(0-3) R(4-7)
0 0111 10rr rrrr
07rr
JZA R
R+1 ( A, skip if zero
0 0111 11rr rrrr
07rr
JZ R
R+1 ( R, skip if zero
0 100b bbrr rrrr
0xxx
BC R,b
0 ( R(b)
0 101b bbrr rrrr
0xxx
BS R,b
1 ( R(b)
0 110b bbrr rrrr
0xxx
JBC R,b
if R(b)=0, skip
0 111b bbrr rrrr
1 00kk kkkk kkkk
1 01kk kkkk kkkk
0xxx
1kkk
1kkk
JBS R,b
CALL k
JMP k
if R(b)=1, skip
PC+1 ( [SP],
(Page, k) ( PC
(Page, k) ( PC
1 1000 kkkk kkkk 18kk
MOV A,k
k(A
1 1001 kkkk kkkk 19kk
OR A,k
A(k(A
1 1010 kkkk kkkk 1Akk
AND A,k
A&k(A
1 1011 kkkk kkkk 1Bkk
XOR A,k
A(k(A
1 1100 kkkk kkkk 1Ckk
RETL k
k ( A, [Top of Stack] ( PC
1 1101 kkkk kkkk 1Dkk
SUB A,k
k-A ( A
1 1110 0000 0010 1E02
INT
PC+ 1 [SP], 001H ( PC
1 1110 1000 kkkk 1E8k
PAGE k
k->R5(3:0)
1 1111 kkkk kkkk 1Fkk
ADD A,k
k+A ( A
STATUS
AFFECTED
C
C
C
None
None
None
None
None 3
None 4
None
None
None
None
None
Z
Z
Z
None
Z, C, DC
None
None
Z, C, DC
3. This instruction is not recommended for RF operation.
4. This instruction cannot operate under RF.
The symbol "R" in the instruction set represents a register designation that specifies
which one of the registers (including operational registers and general purpose
registers) is to be utilized by the instruction.
The symbol "b" represents a bit field designator that selects the value for the bit that is
located in the register "R" and affects operation.
The symbol "k" represents an 8 or 10-bit constant or literal value.
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
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