EM78P569 View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78P569' PDF : 58 Pages View PDF
EM78P569
8-bit OTP Micro-controller
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit 3(CNT1S) : COUNTER1 clock source
0/1 16.384kHz/system clock
Bit 4 ~ Bit 6 (C2_PSC0 ~ C2_PSC2) : COUNTER2 prescaler ratio
C2_PSC2 C2_PSC1 C2_PSC0 COUNTER2
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit 7(CNT2S) : COUNTER2 clock source
0/1 16.384kHz/system clock
IOCE (Interrupt mask)
PAGE0 (Interrupt mask)
7
6
5
4
3
2
1
0
PWM2 RBF
ADI PWM1 /WUP83 /WUP82 /WUP81 /WUP80
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 (/WUP80) : PORT80 wake-up control, 0/1 disable/enable P80 pin wake-up function
Bit 1 (/WUP81) : PORT81 wake-up control, 0/1 disable/enable P81 pin wake-up function
Bit 2 (/WUP82) : PORT82 wake-up control, 0/1 disable/enable P82 pin wake-up function
Bit 3 (/WUP83) : PORT83 wake-up control, 0/1 disable/enable P83 pin wake-up function
Bit 4 (PWM1) : PWM1 interrupt enable bit
0/1 disable/enable interrupt
Bit 5 (ADI) : ADC conversion complete interrupt mask
0/1 disable/enable interrupt
There are four registers for A/D converter. Use one bit of interrupt control register (IOCE PAGE0 Bit5) for
A/D conversion complete interrupt. The status and control register of A/D (IOCB PAGE1 and RE PAGE0
Bit5) responses the A/D conversion status or takes control on A/D. The A/D data register (RB PAGE1)
stores A/D conversion result.
ADI bit in IOCE PAGE0 register is end of A/D conversion complete interrupt enable/disable. It
enables/disables ADI flag in RE register when A/D conversion is complete. ADI flag indicates the end of an
A/D conversion. The A/D converter sets the interrupt flag, ADI in RE PAGE0 register when a conversion is
complete. The interrupt can be disabled by setting ADI bit in IOCE PAGE0 Bit5 to ‘0’.
The A/D converter has six analog input channels AD1~AD6 multiplexed into one sample and hold to A/D
module. Reference voltage can be driven from VREF pin or internal power. The A/D converter itself is of
an 10-bit successive approximation type and produces an 10-bit result in the RB PAGE1 and R7 PAGE1
data register. A conversion is initiated by setting a control bit ADST in IOCB PAGE1 Bit0. Prior to
conversion, the appropriate channel must be selected by setting IN0~IN1 bits in RE register and allowed for
enough time to sample data. Every conversion data of A/D need 12-clock cycle time. The minimum
conversion time required is 13 us (74K sample rate). ADST Bit in IOCB PAGE1 Bit0 must be set to begin a
conversion.
It will be automatically reset in hardware when conversion is complete. At the end of conversion, the
START bit is cleared and the A/D interrupt is activated if ADI in IOCE PAGE0 Bit5 = 1. ADI will be set
when conversion is complete. It can be reset in software.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
38
8/19/2004 V4.4
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