EM78P569 View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78P569' PDF : 58 Pages View PDF
EM78P569
8-bit OTP Micro-controller
The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling
interrupts to avoid recursive interrupts.
VII.8 Instruction Set
Instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O
register.
The symbol "R" represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit,
located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
HEX
0 0000 0000 0000 0000
0 0000 0000 0001 0001
0 0000 0000 0010 0002
0 0000 0000 0011 0003
0 0000 0000 0100 0004
0 0000 0000 rrrr
000r
0 0000 0001 0000 0010
0 0000 0001 0001 0011
0 0000 0001 0010 0012
0 0000 0001 0011 0013
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 0010 0000
0014
001r
0020
0 0000 0011 0000 0030
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
MNEMONIC
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
TBL
INT A
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
OPERATION
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2 bits 9,10 do not
clear
(MR)(+/-)(s/us X)*(s/us
Y) MR
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A VR → A
A VR → R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
STATUS
AFFECTED
None
C
None
T,P
T,P
None
None
None
None
None
None
None
Z,C,DC
None
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Instruction
Cycle**
1
1
1
1
1
1
1
1
2
2
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
43
8/19/2004 V4.4
Share Link: 
