EM78P569 View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78P569' PDF : 58 Pages View PDF
EM78P569
8-bit OTP Micro-controller
VII.5 RESET
The RESET can be caused by
(1) Power on reset
(2) WDT timeout. (if enabled and in GREEN or NORMAL mode)
(3) /RESET pin pull low
Once the RESET occurs, the following functions are performed.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all "0".
• When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
• The Watchdog timer and pre-scaler counter are cleared.
• The Watchdog timer is disabled.
• The CONT register is set to all "1"
• The other register (bit 7 ~ bit 0) default values are as follows.
Operation registers :
Address R register
PAGE0
0x4
00xxxxxx
0x5
xxxx0000
0x6
xxxxxxxx
0x7
xxxxxxxx
0x8
xxxxxxxx
0x9
xxxxxxxx
0xA
00011xx0
0xB
xxxxxxxx
0xC
xxxxxxxx
0xD
xxxxx000
0xE
00000000
0xF
00000000
R register
PAGE1
xxxx0000
xxxxxxxx
xxxx0000
00000000
xxxxxxxx
11111111
xxxxxxxx
00000000
00000000
R register
PAGE2
00000000
xxxxxxxx
0x000000
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
R register
PAGE3
00000000
00000000
xxxxxx00
00000000
00000000
xxxxxx00
00000000
IOC register
PAGE0
IOC register
PAGE1
111x0000
11111111
11111111
11111111
11111111
xxxxxxxx
11111111
11111111
xxxxxxxx
0000xxxx
00000000
00000000
00000000
00000000
00000000
x0xx0xx
000000x0
00000000
00000000
xxxxxxxx
VII.6 Wake-up
The controller provided sleep mode for power saving :
(1) SLEEP mode, RA(7) = 0 + "SLEP" instruction
The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or
PLL control (which has enable register), user has to turn it off by software.
Wake-up from SLEEP mode
(1) WDT time out
(2) External interrupt
(3) /RESET pull low
All these cases will reset controller , and run the program at address zero. The status just like the power on reset.
VII.7 Interrupt
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask
register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the
interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the
interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
42
8/19/2004 V4.4
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