EVAL-AD5382EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5382EBZ' PDF : 40 Pages View PDF
Data Sheet
AD5382
t1
SCLK
SYNC
DIN
t7
t3
t4
t8 t9
DB23
24
t2
DB0 DB23
48
t21
t22
DB0
SDO
INPUT WORD FOR DAC N
t20
INPUT WORD FOR DAC N + 1
DB23
DB0
UNDEFINED
INPUT WORD FOR DAC N
t13
t23
LDAC
Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)
I2C SERIAL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.
Table 5.
Parameter1, 2
fSCL
t1
t2
t3
t4
t5
t6 3
t7
t8
t9
t10
t11
Cb
Limit at TMIN, TMAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1Cb4
400
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS-compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS-compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 Guaranteed by design and characterization, not production tested.
2 See Figure 6.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
Rev. D | Page 11 of 40
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