EVAL-AD5382EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5382EBZ' PDF : 40 Pages View PDF
AD5382
Data Sheet
SDA
t9
t3
t10
t11
t4
SCL
t4
START
CONDITION
t6
t2
t5
t1
t7
REPEATED
START
CONDITION
t8
STOP
CONDITION
Figure 6. I2C-Compatible Serial Interface Timing Diagram
PARALLEL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications Tmin to Tmax,
unless otherwise noted.
Table 6.
Parameter1, 2, 3
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9 4
t104
t114, 5
t12
t13
t14
t15
t16
t17
t18
t19
t20
Limit at TMIN, TMAX
4.5
4.5
20
20
0
0
4.5
4.5
20
700
30
670
30
20
100/2000
20
0
100/2000
2
20
40
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min/max
ns min
ns min
ns min/max
µs typ
ns min
µs max
Description
REG0, REG1, address to WR rising edge setup time
REG0, REG1, address to WR rising edge hold time
CS pulse width low
WR pulse width low
CS to WR falling edge setup time
WR to CS rising edge hold time
Data to WR rising edge setup time
Data to WR rising edge hold time
WR pulse width high
Minimum WR cycle time (single-channel write)
WR rising edge to BUSY falling edge
BUSY pulse width low (single-channel update)
WR rising edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
LDAC rising edge to WR rising edge
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 7.
4 See Figure 28.
5 Measured with the load circuit of Figure 2.
Rev. D | Page 12 of 40
Share Link: 
