EVAL-AD5761RSDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5761RSDZ
Analog Devices
'EVAL-AD5761RSDZ' PDF : 35 Pages View PDF
Data Sheet
AD5761R/AD5721R
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5761R/AD5721R are single channel, 16-/12-bit voltage
output DACs. The AD5761R/AD5721R output ranges are
software selectable and can be configured as follows:
ï‚· Unipolar output voltage: 0 V to 5 V, 0 V to 10 V, 0 V to
16 V, 0 V to 20 V
 Bipolar output voltage: −2.5 V to +7.5 V, ±3 V, ±5 V, ±10 V
Data is written to the AD5761R/AD5721R in a 24-bit word
format via a 4-wire, serial peripheral interface (SPI) compatible,
digital interface. The devices also offer an SDO pin to facilitate
daisy-chaining and readback.
TRANSFER FUNCTION
The internal reference is on by default. The input coding to the
DAC can be straight binary or twos complement (bipolar ranges
case only). Therefore, the transfer function is given by
VOUT
 VREF
ï‚´

M
ï‚´
D
2N

ï€
C


where:
VREF is 2.5 V.
M is the slope for a given output range.
D is the decimal equivalent of the code loaded to the DAC
register as follows:
0 to 4095 for the 12-bit device.
0 to 65,535 for the 16-bit device.
N is the number of bits. N is 12 for the AD5721R and 16 for the
AD5761R.
C is the offset for a given output range.
The values for M and C are as shown in Table 7.
Table 7. M and C Values for Various Output Ranges
Range
M
C
±10 V
8
4
±5 V
4
2
±3 V
2.4
1.2
−2.5 V to +7.5 V
4
1
0 V to 20 V
8
0
0 V to 16 V
6.4
0
0 V to 10 V
4
0
0 V to 5 V
2
0
DAC ARCHITECTURE
The DAC architecture consists of an R-2R DAC followed by an
output buffer amplifier. Figure 72 shows a block diagram of the
DAC architecture. Note that the reference input is buffered
prior to being applied to the DAC. The AD5761R/AD5721R
offer a 2.5 V, 5 ppm/°C maximum internal reference on chip.
The output voltage range obtained from the configurable output
amplifier is selected by writing to the 3 LSBs (RA[2:0]) in the
control register.
V REFIN
DAC REGISTER
VVRREEFFOIUNT/
R- 2R
AGND
AGND
VOUT
CONFIGURABLE
OUTPUT
AMPLIFIER
OUTPUT
RANGE CONTROL
Figure 72. DAC Architecture
R-2R DAC
The architecture of the AD5761R consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 73. The
6 MSBs of the 16-bit data-word are decoded to drive 63 switches,
E0 to E62, while the remaining 10 bits of the data-word drive
the S0 to S9 switches of a 10-bit voltage mode R-2R ladder
network.
The code loaded into the DAC register determines which arms
of the ladder are switched between VREF and ground (AGND).
The output voltage is taken from the end of the ladder and
amplified afterwards to provide the selected output voltage.
RR
R
2R 2R
S0
2R ... 2R
S1 ... S9
VOUT
2R
2R ... 2R
E62 E61 ... E0
VREF
AGND
10-BIT R-2R LADDER
6 MSBs DECODED INTO
63 EQUAL SEGMENTS
Figure 73. DAC Ladder Structure
Internal Reference
The AD5761R/AD5721R feature an on-chip reference. The
on-chip reference is on at power-up, and this reference can be
turned off by setting the software-programmable bit, DB5, in
the control register. Table 12 shows how the state of the bit
corresponds to the mode of operation.
The internal reference is available at the V /V RFEFIN REFOUT pin.
A buffer is required if the reference output is used to drive
external loads. Place a capacitor in the range of 1 nF to 100 nF
between the reference output and DGND to improve the noise
performance.
Reference Buffer
The AD5761R/AD5721R can operate with either an external or
internal reference. The reference input has an input range of 2 V
to 3 V with 2.5 V for specified performance. This input voltage
is then buffered before it is applied to the DAC core.
Rev. C | Page 25 of 36
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